FIG. 1 illustrates a half-bridge circuit with two transistors T1 and T2, each of which has a load path D-8 and a control gate G. The transistors T1 and T2 are implemented in the example as n-channel MOSFETs, whose drain-source paths D-8 form the load paths and whose gate terminals form the control terminals. A node that is shared by the load paths in the transistors T1 and T2 constitutes an output OUT of the half-bridge circuit. The half-bridge circuit with the two transistors T1 and T2 is used to control a load connected to the output terminal OUT, as shown in FIG. 1 by a dashed line, and which is implemented as an LC circuit, for example.
The transistors T1 and T2 are driven in accordance with the first and second control signals S1 and S2, which are generated by a control circuit that is not described here, and which are converted by means of driver stages 21 and 22 to suitable drive voltages Vgs1 and Vgs2 for driving the MOSFETs T1 and T2. These drive voltages are the gate-source voltages for the transistors T1 and T2 designed as MOSFETs.
The load paths of the transistors T1 and T2 are connected in series between a terminal for first power supply potential or—positive supply potential VCC and a terminal for negative supply potential or reference potential GND. To prevent cross current between the terminals for the positive supply potential VCC and reference potential GND, the first and second transistors T1 and T2 must be driven in such a way that the two transistors T1 and T2 are not operating in the conducting state together at any time. Note here that the transistors T1 and T2 react in a delayed manner to changes in level of the control signals S1 and S2 by changing their current switching state. This is mainly due to the fact that internal gate-source capacitors Cgs1 and Cgs2 (displayed by dashed lines) of the MOSFETs T1 and T2 must first be charged from a switch-off level to a switch-on level after a change in level of the corresponding control signal until the corresponding MOSFET T1 or T2 actually conducts, and that internal gate-source capacitors Cgs1 and Cgs2 must be discharged from a switch-on level to a switch-off level after a change in level of the control signal until the corresponding MOSFET actually blocks.
A known method of preventing cross currents is to prevent generating a switch-on level for a control signal until after a delay has elapsed after the other control signal has reached a switch-off level. This is illustrated in FIG. 2.
FIG. 2 gives an example of the timing of the first control signal S1 for the first transistor T1. The control signal S1 is a dual-value signal that can reach switch-on and switch-off levels. The switch-on level is the level of the signal at which the first transistor T1 is to be driven as conducting, while the switch-off level is the level of the signal at which the first transistor T1 is to be driven as blocking. This first control signal S1 switches at a time t10 from the switch-on level to the switch-off level. The switch-on level of the second control signal S2 occurs at a time t11 after a delay T0 after the time t10. The delay T0 must be selected so that the transistor T1 driven by the first control signal S1 is certain to be switched off—i.e., operates in the blocking state, within the delay period T0.
In order to be sure of avoiding cross currents, the delay T0 could be configured to be very long. However, using the half-bridge circuit to control an inductive load as illustrated in FIG. 1 has the disadvantage that during the period in which the first transistor T1 is already blocking, but the second transistor T2 has not yet been driven to conducting mode, a body diode integrated into the second MOSFET T2 (the diode marked with the reference D2 in FIG. 1) adopts a free-wheeling current of the inductive load L. Greater losses occur here in comparison with the operating case in which the second transistor T2 is conducting and receiving the free-wheeling current. Considerable power losses may result in this way in the event of high switching frequencies. To minimize such losses, the period during which the two transistors T1 and T2 are blocking at the same time should be as short as possible.
A proposal can be found in DE 101 47 882 A1 to prevent cross currents by monitoring the switching states of two transistors of a half-bridge circuit by determining the relevant driving currents and not driving one of the two transistors into the conducting state until it has been ascertained that the second transistor is in a blocking state.
The switching state of a MOSFET can also be determined by monitoring its gate-source voltage. However, this can have the problem in the case of power MOSFETs accommodated in a chip housing that the voltage on the outside of the housing can differ from the actual drive voltage in the component. It could therefore be the case that the MOSFET is still conducting although the voltage detected on the outside indicates that the component is in a blocking state.
Data sheet UCC 27223, Texas Instruments, December 2003, discloses a driver circuit for driving a half bridge including a low-side MOSFET and a high-side MOSFET in a buck converter. The driver circuit is adapted to detect body-diode conduction of the low-side MOSFET and is adapted to minimize the dead time, i.e. the time when both MOSFETs are blocking, based on the body-diode conduction time.
Accordingly, it would be advantageous to provide a method of driving the first transistor in a half-bridge circuit containing the first transistor and a second transistor with which cross currents can be prevented, and of minimizing the delay during which the first and second transistors are blocking at the same time. It would of further advantage to provide a control circuit for a half-bridge circuit for use with such method.